Hardware for parallel command list generation

ABSTRACT

A method for providing state inheritance across command lists in a multi-threaded processing environment. The method includes receiving an application program that includes a plurality of parallel threads; generating a command list for each thread of the plurality of parallel threads; causing a first command list associated with a first thread of the plurality of parallel threads to be executed by a processing unit; and causing a second command list associated with a second thread of the plurality of parallel threads to be executed by the processing unit, where the second command list inherits from the first command list state associated with the processing unit.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional of U.S. patent application Ser. No.12/853,161, filed Aug. 9, 2010 (Attorney Docket No.NVDA/SC-09-0321-US0-US2), which relates to and claims benefit of U.S.Provisional Patent Application Ser. No. 61/245,174, filed on Sep. 23,2009.

BACKGROUND

1. Field of the Invention

The present invention relates to processing units and, in particular, tohardware for parallel command list generation.

2. Description of the Related Art

Microsoft® Direct3D 11 (DX11) is an API (Application ProgrammingInterface) that supports tessellation and allows for improvedmulti-threading to assist developers in developing applications thatbetter utilize multi-core processors.

In DX11, each core of a CPU (central processing unit) can executethreads of commands in parallel. Each core, or different threads on thesame core, generates a separate command list via its own copy of auser-mode driver to increase performance of the software application. Acommand list is an API-level abstraction of a command buffer, which is alower-level concept. The driver builds up a command buffer as itreceives API commands from the application; a command list is manifestedby a completed command buffer plus any additional implementation-definedmeta information. The contents of a command list or command buffer aretypically executed by a GPU (graphics processing unit). There is asingle thread running on one of the CPU cores that submits command listsfor execution in a particular order. The order of the command lists, andtherefore the order of the command buffers, is determined by theapplication program. Command buffers are fed into the core viapushbuffers. The command buffers are composed of methods to be executedby the core, typically a GPU.

However, DX11 does not allow processor state inheritance across commandlists. Instead, the processor state is reset at the beginning of everycommand list to a so-called “clean slate state.” That means that eachuser-mode driver thread sets all the state parameters in the processorat the beginning of the command list. Not providing state inheritanceacross command lists provides a significant drawback since threadscannot cooperate when executing the application program. Moreover, theadded processing cost of resetting the processor state to the cleanslate state using dozens or hundreds of commands adds inefficiencies tothe system, thereby reducing overall performance.

As the foregoing illustrates, there is a need in the art for an improvedtechnique that addresses the limitations of current approaches set forthabove.

SUMMARY

One embodiment of the invention provides a method for providing stateinheritance across command lists in a multi-threaded processingenvironment. The method includes receiving an application program thatincludes a plurality of parallel threads; generating a command list foreach thread of the plurality of parallel threads; causing a firstcommand list associated with a first thread of the plurality of parallelthreads to be executed by a processing unit; and causing a secondcommand list associated with a second thread of the plurality ofparallel threads to be executed by the processing unit, where the secondcommand list inherits from the first command list state associated withthe processing unit.

Another embodiment of the invention provides a method for providing aninitial default state for a multi-threaded processing environment. Themethod includes receiving an application program that includes aplurality of parallel threads; generating a command list for each threadof the plurality of parallel threads; inserting an unbind method into afirst command list associated with a first thread of the plurality ofparallel threads to be executed by a processing unit, where the unbindmethod is a command to be executed by the processing unit; causing theunbind method to be executed by the processing unit, resulting in eachparameter of the state of a processing unit being reset; and causingcommands included in the first command list to be executed by theprocessing unit after the unbind method is executed.

One advantage provided by embodiments of the invention is that betterprocessing efficiency is achieved relative to prior art techniques.

BRIEF DESCRIPTION OF THE DRAWINGS

So that the manner in which the above recited features of the presentinvention can be understood in detail, a more particular description ofthe invention, briefly summarized above, may be had by reference toembodiments, some of which are illustrated in the appended drawings. Itis to be noted, however, that the appended drawings illustrate onlytypical embodiments of this invention and are therefore not to beconsidered limiting of its scope, for the invention may admit to otherequally effective embodiments.

FIG. 1 is a block diagram illustrating a computer system configured toimplement one or more aspects of the present invention;

FIG. 2 is a block diagram of a parallel processing subsystem for thecomputer system of FIG. 1, according to one embodiment of the presentinvention;

FIG. 3A is a block diagram of a GPC within one of the PPUs of FIG. 2,according to one embodiment of the present invention;

FIG. 3B is a block diagram of a partition unit within one of the PPUs ofFIG. 2, according to one embodiment of the present invention; and

FIG. 4 is a conceptual diagram of a graphics processing pipeline thatone or more of the PPUs of FIG. 2 can be configured to implement,according to one embodiment of the present invention.

FIG. 5 is a conceptual diagram illustrating multi-threaded processingusing parallel command lists, according to one embodiment of theinvention.

FIG. 6 is a conceptual diagram that illustrates state inheritance acrosscommand lists, according to one embodiment of the invention.

FIG. 7 is a conceptual diagram illustrating a command list for stateinheritance, according to one embodiment of the invention.

FIG. 8 is a flow diagram of method steps for multi-threaded processingwith state inheritance across command lists, according to one embodimentof the invention.

FIG. 9 is a flow diagram of method steps for generating a command list,according to one embodiment of the invention.

FIG. 10 is a flow diagram of method steps for implementingmulti-threaded processing using an UnbindAll( ) method, according to oneembodiment of the invention.

DETAILED DESCRIPTION

In the following description, numerous specific details are set forth toprovide a more thorough understanding of the present invention. However,it will be apparent to one of skill in the art that the presentinvention may be practiced without one or more of these specificdetails. In other instances, well-known features have not been describedin order to avoid obscuring the present invention.

System Overview

FIG. 1 is a block diagram illustrating a computer system 100 configuredto implement one or more aspects of the present invention. Computersystem 100 includes a central processing unit (CPU) 102 and a systemmemory 104 communicating via a bus path through a memory bridge 105. TheDX11 multi-threading features are primarily aimed at multi-core CPUs.Thus, in some embodiments, the CPU 102 is a multi-core CPU. Memorybridge 105 may be integrated into CPU 102 as shown in FIG. 1.Alternatively, memory bridge 105, may be a conventional device, e.g., aNorthbridge chip, that is connected via a bus to CPU 102. Memory bridge105 is connected via communication path 106 (e.g., a HyperTransportlink) to an I/O (input/output) bridge 107. I/O bridge 107, which may be,e.g., a Southbridge chip, receives user input from one or more userinput devices 108 (e.g., keyboard, mouse) and forwards the input to CPU102 via path 106 and memory bridge 105. A parallel processing subsystem112 is coupled to memory bridge 105 via a bus or other communicationpath 113 (e.g., a PCI Express, Accelerated Graphics Port, orHyperTransport link); in one embodiment parallel processing subsystem112 is a graphics subsystem that delivers pixels to a display device 110(e.g., a conventional CRT or LCD based monitor). A system disk 114 isalso connected to I/O bridge 107. A switch 116 provides connectionsbetween I/O bridge 107 and other components such as a network adapter118 and various add-in cards 120 and 121. Other components (notexplicitly shown), including USB or other port connections, CD drives,DVD drives, film recording devices, and the like, may also be connectedto I/O bridge 107. Communication paths interconnecting the variouscomponents in FIG. 1 may be implemented using any suitable protocols,such as PCI (Peripheral Component Interconnect), PCI-Express (PCI-E),AGP (Accelerated Graphics Port), HyperTransport, or any other bus orpoint-to-point communication protocol(s), and connections betweendifferent devices may use different protocols as is known in the art.

In one embodiment, the parallel processing subsystem 112 incorporatescircuitry optimized for graphics and video processing, including, forexample, video output circuitry, and constitutes a graphics processingunit (GPU). In another embodiment, the parallel processing subsystem 112incorporates circuitry optimized for general purpose processing, whilepreserving the underlying computational architecture, described ingreater detail herein. In yet another embodiment, the parallelprocessing subsystem 112 may be integrated with one or more other systemelements, such as the memory bridge 105, CPU 102, and I/O bridge 107 toform a system on chip (SoC).

It will be appreciated that the system shown herein is illustrative andthat variations and modifications are possible. The connection topology,including the number and arrangement of bridges, may be modified asdesired. For instance, in some embodiments, system memory 104 isconnected to CPU 102 directly rather than through a bridge, and otherdevices communicate with system memory 104 via memory bridge 105 and CPU102. In other alternative topologies, parallel processing subsystem 112is connected to I/O bridge 107 or directly to CPU 102, rather than tomemory bridge 105. In still other embodiments, one or more of CPU 102,I/O bridge 107, parallel processing subsystem 112, and memory bridge 105may be integrated into one or more chips. The particular componentsshown herein are optional; for instance, any number of add-in cards orperipheral devices might be supported. In some embodiments, switch 116is eliminated, and network adapter 118 and add-in cards 120, 121 connectdirectly to I/O bridge 107.

FIG. 2 illustrates a parallel processing subsystem 112, according to oneembodiment of the present invention. As shown, parallel processingsubsystem 112 includes one or more parallel processing units (PPUs) 202,each of which is coupled to a local parallel processing (PP) memory 204.In general, a parallel processing subsystem includes a number U of PPUs,where U ≧1. (Herein, multiple instances of like objects are denoted withreference numbers identifying the object and parenthetical numbersidentifying the instance where needed.) PPUs 202 and parallel processingmemories 204 may be implemented using one or more integrated circuitdevices, such as programmable processors, application specificintegrated circuits (ASICs), or memory devices, or in any othertechnically feasible fashion.

Referring again to FIG. 1, in some embodiments, some or all of PPUs 202in parallel processing subsystem 112 are graphics processors withrendering pipelines that can be configured to perform various tasksrelated to generating pixel data from graphics data supplied by CPU 102and/or system memory 104, interacting with local parallel processingmemory 204 (which can be used as graphics memory including, e.g., aconventional frame buffer) to store and update pixel data, deliveringpixel data to display device 110, and the like. In some embodiments,parallel processing subsystem 112 may include one or more PPUs 202 thatoperate as graphics processors and one or more other PPUs 202 that areused for general-purpose computations. The PPUs may be identical ordifferent, and each PPU may have its own dedicated parallel processingmemory device(s) or no dedicated parallel processing memory device(s).One or more PPUs 202 may output data to display device 110 or each PPU202 may output data to one or more display devices 110.

In operation, CPU 102 is the master processor of computer system 100,controlling and coordinating operations of other system components. Inparticular, CPU 102 issues commands that control the operation of PPUs202. In some embodiments, CPU 102 writes a stream of commands for eachPPU 202 to a command buffer (not explicitly shown in either FIG. 1 orFIG. 2) that may be located in system memory 104, parallel processingmemory 204, or another storage location accessible to both CPU 102 andPPU 202. PPU 202 reads the command stream from the command buffer andthen executes commands asynchronously relative to the operation of CPU102. CPU 102 may also create data buffers that PPUs 202 may read inresponse to commands in the command buffer. Each command and data buffermay be read by each of PPUs 202.

Referring back now to FIG. 2, each PPU 202 includes an I/O(input/output) unit 205 that communicates with the rest of computersystem 100 via communication path 113, which connects to memory bridge105 (or, in one alternative embodiment, directly to CPU 102). Theconnection of PPU 202 to the rest of computer system 100 may also bevaried. In some embodiments, parallel processing subsystem 112 isimplemented as an add-in card that can be inserted into an expansionslot of computer system 100. In other embodiments, a PPU 202 can beintegrated on a single chip with a bus bridge, such as memory bridge 105or I/O bridge 107. In still other embodiments, some or all elements ofPPU 202 may be integrated on a single chip with CPU 102.

In one embodiment, communication path 113 is a PCI-Express link, inwhich dedicated lanes are allocated to each PPU 202, as is known in theart. Other communication paths may also be used. An I/O unit 205generates packets (or other signals) for transmission on communicationpath 113 and also receives all incoming packets (or other signals) fromcommunication path 113, directing the incoming packets to appropriatecomponents of PPU 202. For example, commands related to processing tasksmay be directed to a host interface 206, while commands related tomemory operations (e.g., reading from or writing to parallel processingmemory 204) may be directed to a memory crossbar unit 210. Hostinterface 206 reads each command buffer and outputs the work specifiedby the command buffer to a front end 212.

Each PPU 202 advantageously implements a highly parallel processingarchitecture. As shown in detail, PPU 202(0) includes a processingcluster array 230 that includes a number C of general processingclusters, (GPCs) 208, where C ≧1. Each GPC 208 is capable of executing alarge number (e.g., hundreds or thousands) of threads concurrently,where each thread is an instance of a program. In various applications,different GPCs 208 may be allocated for processing different types ofprograms or for performing different types of computations. For example,in a graphics application, a first set of GPCs 208 may be allocated toperform tessellation operations and to produce primitive topologies forpatches, and a second set of GPCs 208 may be allocated to performtessellation shading to evaluate patch parameters for the primitivetopologies and to determine vertex positions and other per-vertexattributes. The allocation of GPCs 208 may vary depending on theworkload arising for each type of program or computation. Alternatively,GPCs 208 may be allocated to perform processing tasks using a time-slicescheme to switch between different processing tasks.

GPCs 208 receive processing tasks to be executed via a work distributionunit 200, which receives commands defining processing tasks from frontend unit 212. Processing tasks include pointers to data to be processed,e.g., surface (patch) data, primitive data, vertex data, and/or pixeldata, as well as state parameters and commands defining how the data isto be processed (e.g., what program is to be executed). Workdistribution unit 200 may be configured to fetch the pointerscorresponding to the processing tasks, may receive the pointers fromfront end 212, or may receive the data directly from front end 212. Insome embodiments, indices specify the location of the data in an array.Front end 212 ensures that GPCs 208 are configured to a valid statebefore the processing specified by the command buffers is initiated.

When PPU 202 is used for graphics processing, for example, theprocessing workload for each patch is divided into approximately equalsized tasks to enable distribution of the tessellation processing tomultiple GPCs 208. A work distribution unit 200 may be configured tooutput tasks at a frequency capable of providing tasks to multiple GPCs208 for processing. In some embodiments of the present invention,portions of GPCs 208 are configured to perform different types ofprocessing. For example a first portion may be configured to performvertex shading and topology generation, a second portion may beconfigured to perform tessellation and geometry shading, and a thirdportion may be configured to perform pixel shading in screen space toproduce a rendered image. The ability to allocate portions of GPCs 208for performing different types of processing tasks efficientlyaccommodates any expansion and contraction of data produced by thosedifferent types of processing tasks. Intermediate data produced by GPCs208 may be buffered to allow the intermediate data to be transmittedbetween GPCs 208 with minimal stalling in cases where the rate at whichdata is accepted by a downstream GPC 208 lags the rate at which data isproduced by an upstream GPC 208.

Memory interface 214 may be partitioned into a number D of memorypartition units that are each coupled to a portion of parallelprocessing memory 204, where D ≧1. Each portion of parallel processingmemory 204 generally includes one or more memory devices (e.g DRAM 220).Persons skilled in the art will appreciate that DRAM 220 may be replacedwith other suitable storage devices and can be of generally conventionaldesign. A detailed description is therefore omitted. Render targets,such as frame buffers or texture maps may be stored across DRAMs 220,allowing partition units 215 to write portions of each render target inparallel to efficiently use the available bandwidth of parallelprocessing memory 204.

Any one of GPCs 208 may process data to be written to any of the DRAMs220 within parallel processing memory 204. Crossbar unit 210 isconfigured to route the output of each GPC 208 to the input of anypartition unit 215 or to another GPC 208 for further processing. GPCs208 communicate with memory interface 214 through crossbar unit 210 toread from or write to various external memory devices. In oneembodiment, crossbar unit 210 has a connection to memory interface 214to communicate with I/O unit 205, as well as a connection to localparallel processing memory 204, thereby enabling the processing coreswithin the different GPCs 208 to communicate with system memory 104 orother memory that is not local to PPU 202. Crossbar unit 210 may usevirtual channels to separate traffic streams between the GPCs 208 andpartition units 215.

Again, GPCs 208 can be programmed to execute processing tasks relatingto a wide variety of applications, including but not limited to, linearand nonlinear data transforms, filtering of video and/or audio data,modeling operations (e.g., applying laws of physics to determineposition, velocity and other attributes of objects), image renderingoperations (e.g., tessellation shader, vertex shader, geometry shader,and/or pixel shader programs), and so on. PPUs 202 may transfer datafrom system memory 104 and/or local parallel processing memories 204into internal (on-chip) memory, process the data, and write result databack to system memory 104 and/or local parallel processing memories 204,where such data can be accessed by other system components, includingCPU 102 or another parallel processing subsystem 112.

A PPU 202 may be provided with any amount of local parallel processingmemory 204, including no local memory, and may use local memory andsystem memory in any combination. For instance, a PPU 202 can be agraphics processor in a unified memory architecture (UMA) embodiment. Insuch embodiments, little or no dedicated graphics (parallel processing)memory would be provided, and PPU 202 would use system memoryexclusively or almost exclusively. In UMA embodiments, a PPU 202 may beintegrated into a bridge chip or processor chip or provided as adiscrete chip with a high-speed link (e.g., PCI-Express) connecting thePPU 202 to system memory via a bridge chip or other communication means.

As noted above, any number of PPUs 202 can be included in a parallelprocessing subsystem 112. For instance, multiple PPUs 202 can beprovided on a single add-in card, or multiple add-in cards can beconnected to communication path 113, or one or more PPUs 202 can beintegrated into a bridge chip. PPUs 202 in a multi-PPU system may beidentical to or different from one another. For instance, different PPUs202 might have different numbers of processing cores, different amountsof local parallel processing memory, and so on. Where multiple PPUs 202are present, those PPUs may be operated in parallel to process data at ahigher throughput than is possible with a single PPU 202. Systemsincorporating one or more PPUs 202 may be implemented in a variety ofconfigurations and form factors, including desktop, laptop, or handheldpersonal computers, servers, workstations, game consoles, embeddedsystems, and the like.

Processing Cluster Array Overview

FIG. 3A is a block diagram of a GPC 208 within one of the PPUs 202 ofFIG. 2, according to one embodiment of the present invention. Each GPC208 may be configured to execute a large number of threads in parallel,where the term “thread” refers to an instance of a particular programexecuting on a particular set of input data. In some embodiments,single-instruction, multiple-data (SIMD) instruction issue techniquesare used to support parallel execution of a large number of threadswithout providing multiple independent instruction units. In otherembodiments, single-instruction, multiple-thread (SIMT) techniques areused to support parallel execution of a large number of generallysynchronized threads, using a common instruction unit configured toissue instructions to a set of processing engines within each one of theGPCs 208. Unlike a SIMD execution regime, where all processing enginestypically execute identical instructions, SIMT execution allowsdifferent threads to more readily follow divergent execution pathsthrough a given thread program. Persons skilled in the art willunderstand that a SIMD processing regime represents a functional subsetof a SIMT processing regime.

In graphics applications, a GPC 208 may be configured to implement aprimitive engine for performing screen space graphics processingfunctions that may include, but are not limited to primitive setup,rasterization, and z culling. The primitive engine receives a processingtask from work distribution unit 200, and when the processing task doesnot require the operations performed by primitive engine, the processingtask is passed through the primitive engine to a pipeline manager 305.Operation of GPC 208 is advantageously controlled via a pipeline manager305 that distributes processing tasks to streaming multiprocessors(SPMs) 310. Pipeline manager 305 may also be configured to control awork distribution crossbar 330 by specifying destinations for processeddata output by SPMs 310.

In one embodiment, each GPC 208 includes a number M of SPMs 310, where M≧1, each SPM 310 configured to process one or more thread groups. Theseries of instructions transmitted to a particular GPC 208 constitutes athread, as previously defined herein, and the collection of a certainnumber of concurrently executing threads across the parallel processingengines (not shown) within an SPM 310 is referred to herein as a “threadgroup.” As used herein, a “thread group” refers to a group of threadsconcurrently executing the same program on different input data, witheach thread of the group being assigned to a different processing enginewithin an SPM 310. A thread group may include fewer threads than thenumber of processing engines within the SPM 310, in which case someprocessing engines will be idle during cycles when that thread group isbeing processed. A thread group may also include more threads than thenumber of processing engines within the SPM 310, in which caseprocessing will take place over multiple clock cycles. Since each SPM310 can support up to G thread groups concurrently, it follows that upto G×M thread groups can be executing in GPC 208 at any given time.

Additionally, a plurality of related thread groups may be active (indifferent phases of execution) at the same time within an SPM 310. Thiscollection of thread groups is referred to herein as a “cooperativethread array” (“CTA”). The size of a particular CTA is equal to m*k,where k is the number of concurrently executing threads in a threadgroup and is typically an integer multiple of the number of parallelprocessing engines within the SPM 310, and m is the number of threadgroups simultaneously active within the SPM 310. The size of a CTA isgenerally determined by the programmer and the amount of hardwareresources, such as memory or registers, available to the CTA.

An exclusive local address space is available to each thread, and ashared per-CTA address space is used to pass data between threads withina CTA. Data stored in the per-thread local address space and per-CTAaddress space is stored in L1 cache 320, and an eviction policy may beused to favor keeping the data in L1 cache 320. Each SPM 310 uses spacein a corresponding L1 cache 320 that is used to perform load and storeoperations. Each SPM 310 also has access to L2 caches within thepartition units 215 that are shared among all GPCs 208 and may be usedto transfer data between threads. Finally, SPMs 310 also have access tooff-chip “global” memory, which can include, e.g., parallel processingmemory 204 and/or system memory 104. An L2 cache may be used to storedata that is written to and read from global memory. It is to beunderstood that any memory external to PPU 202 may be used as globalmemory.

Also, each SPM 310 advantageously includes an identical set offunctional units (e.g., arithmetic logic units, etc.) that may bepipelined, allowing a new instruction to be issued before a previousinstruction has finished, as is known in the art. Any combination offunctional units may be provided. In one embodiment, the functionalunits support a variety of operations including integer and floatingpoint arithmetic (e.g., addition and multiplication), comparisonoperations, Boolean operations (AND, OR, XOR), bit-shifting, andcomputation of various algebraic functions (e.g., planar interpolation,trigonometric, exponential, and logarithmic functions, etc.); and thesame functional-unit hardware can be leveraged to perform differentoperations.

Each GPC 208 may include a memory management unit (MMU) 328 that isconfigured to map virtual addresses into physical addresses. In otherembodiments, MMU(s) 328 may reside within the memory interface 214. TheMMU 328 includes a set of page table entries (PTEs) used to map avirtual address to a physical address of a tile and optionally a cacheline index. The physical address is processed to distribute surface dataaccess locality to allow efficient request interleaving among partitionunits. The cache line index may be used to determine whether of not arequest for a cache line is a hit or miss.

In graphics applications, a GPC 208 may be configured such that each SPM310 is coupled to a texture unit 315 for performing texture mappingoperations, e.g., determining texture sample positions, reading texturedata, and filtering the texture data. Texture data is read via memoryinterface 214 and is fetched from an L2 cache, parallel processingmemory 204, or system memory 104, as needed. Texture unit 315 may beconfigured to store the texture data in an internal cache. In someembodiments, texture unit 315 is coupled to L1 cache 320, and texturedata is stored in L1 cache 320. Each SPM 310 outputs processed tasks towork distribution crossbar 330 in order to provide the processed task toanother GPC 208 for further processing or to store the processed task inan L2 cache, parallel processing memory 204, or system memory 104 viacrossbar unit 210. A preROP (pre-raster operations) 325 is configured toreceive data from SPM 310, direct data to ROP units within partitionunits 215, and perform optimizations for color blending, organize pixelcolor data, and perform address translations.

It will be appreciated that the core architecture described herein isillustrative and that variations and modifications are possible. Anynumber of processing engines, e.g., primitive engines, SPMs 310, textureunits 315, or preROPs 325 may be included within a GPC 208. Further,while only one GPC 208 is shown, a PPU 202 may include any number ofGPCs 208 that are advantageously functionally similar to one another sothat execution behavior does not depend on which GPC 208 receives aparticular processing task. Further, each GPC 208 advantageouslyoperates independently of other GPCs 208 using separate and distinctprocessing engines, L1 caches 320, and so on.

FIG. 3B is a block diagram of a partition unit 215 within one of thePPUs 202 of FIG. 2, according to one embodiment of the presentinvention. As shown, partition unit 215 includes a L2 cache 350, a framebuffer (FB) 355, and a raster operations unit (RO) 360. L2 cache 350 isa read/write cache that is configured to perform load and storeoperations received from crossbar unit 210 and ROP 360. Read misses andurgent writeback requests are output by L2 cache 350 to FB 355 forprocessing. Dirty updates are also sent to FB 355 for opportunisticprocessing. FB 355 interfaces directly with DRAM 220, outputting readand write requests and receiving data read from DRAM 220.

In graphics applications, ROP 360 is a processing unit that performsraster operations, such as stencil, z test, blending, and the like, andoutputs pixel data as processed graphics data for storage in graphicsmemory. In some embodiments of the present invention, ROP 360 isincluded within each GPC 208 instead of partition unit 215, and pixelread and write requests are transmitted over crossbar unit 210 insteadof pixel fragment data.

The processed graphics data may be displayed on display device 110 orrouted for further processing by CPU 102 or by one of the processingentities within parallel processing subsystem 112. Each partition unit215 includes a ROP 360 in order to distribute processing of the rasteroperations. In some embodiments, ROP 360 may be configured to compress zor color data that is written to memory and decompress z or color datathat is read from memory.

Persons skilled in the art will understand that the architecturedescribed in FIGS. 1, 2, 3A and 3B in no way limits the scope of thepresent invention and that the techniques taught herein may beimplemented on any properly configured processing unit, including,without limitation, one or more CPUs, one or more multi-core CPUs, oneor more PPUs 202, one or more GPCs 208, one or more graphics or specialpurpose processing units, or the like, without departing the scope ofthe present invention.

FIG. 4 is a conceptual diagram of a graphics processing pipeline 400,that one or more of the PPUs 202 of FIG. 2 can be configured toimplement, according to one embodiment of the present invention. Forexample, one of the SPMs 310 may be configured to perform the functionsof one or more of a vertex processing unit 415, a geometry processingunit 425, and a fragment processing unit 460. The functions of dataassembler 410, primitive assembler 420, rasterizer 455, and rasteroperations unit 465 may also be performed by other processing engineswithin a GPC 208 and a corresponding partition unit 215. Alternately,graphics processing pipeline 400 may be implemented using dedicatedprocessing units for one or more functions.

Data assembler 410 processing unit collects vertex data for high-ordersurfaces, primitives, and the like, and outputs the vertex data,including the vertex attributes, to vertex processing unit 415. Vertexprocessing unit 415 is a programmable execution unit that is configuredto execute vertex shader programs, lighting and transforming vertex dataas specified by the vertex shader programs. For example, vertexprocessing unit 415 may be programmed to transform the vertex data froman object-based coordinate representation (object space) to analternatively based coordinate system such as world space or normalizeddevice coordinates (NDC) space. Vertex processing unit 415 may read datathat is stored in L1 cache 320, parallel processing memory 204, orsystem memory 104 by data assembler 410 for use in processing the vertexdata.

Primitive assembler 420 receives vertex attributes from vertexprocessing unit 415, reading stored vertex attributes, as needed, andconstructs graphics primitives for processing by geometry processingunit 425. Graphics primitives include triangles, line segments, points,and the like. Geometry processing unit 425 is a programmable executionunit that is configured to execute geometry shader programs,transforming graphics primitives received from primitive assembler 420as specified by the geometry shader programs. For example, geometryprocessing unit 425 may be programmed to subdivide the graphicsprimitives into one or more new graphics primitives and calculateparameters, such as plane equation coefficients, that are used torasterize the new graphics primitives.

In some embodiments, geometry processing unit 425 may also add or deleteelements in the geometry stream. Geometry processing unit 425 outputsthe parameters and vertices specifying new graphics primitives to aviewport scale, cull, and clip unit 450. Geometry processing unit 425may read data that is stored in parallel processing memory 204 or systemmemory 104 for use in processing the geometry data. Viewport scale,cull, and clip unit 450 performs clipping, culling, and viewport scalingand outputs processed graphics primitives to a rasterizer 455.

Rasterizer 455 scan converts the new graphics primitives and outputsfragments and coverage data to fragment processing unit 460.Additionally, rasterizer 455 may be configured to perform z culling andother z-based optimizations.

Fragment processing unit 460 is a programmable execution unit that isconfigured to execute fragment shader programs, transforming fragmentsreceived from rasterizer 455, as specified by the fragment shaderprograms. For example, fragment processing unit 460 may be programmed toperform operations such as perspective correction, texture mapping,shading, blending, and the like, to produce shaded fragments that areoutput to raster operations unit 465. Fragment processing unit 460 mayread data that is stored in parallel processing memory 204 or systemmemory 104 for use in processing the fragment data. Fragments may beshaded at pixel, sample, or other granularity, depending on theprogrammed sampling rate.

Raster operations unit 465 is a processing unit that performs rasteroperations, such as stencil, z test, blending, and the like, and outputspixel data as processed graphics data for storage in graphics memory.The processed graphics data may be stored in graphics memory, e.g.,parallel processing memory 204, and/or system memory 104, for display ondisplay device 110 or for further processing by CPU 102 or parallelprocessing subsystem 112. In some embodiments of the present invention,raster operations unit 465 is configured to compress z or color datathat is written to memory and decompress z or color data that is readfrom memory.

Hardware for Parallel Command List Generation

Embodiments of the invention are related to carrying over the processorstate from one command list to the next in a multi-threaded processingsystem. That is, the state in the processor, such as a GPU or CPU, isaccumulated across multiple command lists. This feature is also referredto as “state inheritance across command lists.” State inheritance acrosscommand lists presents a significant problem for the driver because thedecision of which methods to put into the command list is dependent onthe GPU state at the time the method is executed in the GPU. The GPUstate is, in essence, the accumulated state present in all commandbuffers that have previously executed. However, the GPU state could beset in a previous command buffer generated by a different driver threadthat has not yet completed building that previous command buffer.Embodiments of the invention either remove the dependency on unknowninherited state or update state-dependent portions of command buffersonce the inherited state is known.

In one embodiment, the processing state is defined as the set ofparameters associated with a processing unit that executes commands.Examples of parameters included in the processing state include aselection of a vertex shader, a geometry shader, a pixel shader, or thelike, one or more parameters defining a set of different textures boundto the pixel shader, a parameter defining how blending is performed, alist of target rendering surfaces, among others. A “method,” as usedherein, is a command sent to the processing hardware that sets one ormore of the parameters defining the processor state. In oneimplementation, setting the processor state defines how differentprocessing stages execute subsequent commands.

Embodiments of the invention attempt to eliminate the situations wherethe methods put into a command list are dependent on the current statein the execution-order of all the command lists of the GPU. This featureis referred to as “making the driver stateless,” in that the driver doesnot need to consider the current GPU state when generating a commandlist.

Another motivation for embodiments of the invention is to reduce the CPUoverhead of submitting rendering commands from the application to thehardware, i.e., to keep the CPU from becoming a bottleneck. The reasonfor this overhead is that it takes time to examine the current state todetermine which methods to send. Less overhead is required if themethods can be written without having to inspect current state.

In one embodiment, there is one master thread and multiple workerthreads per processing device. For example, this 1-master/N-workersarrangement may be determined by the application. Each worker thread“owns” a command list that is associated with commands to be executed bythe processing device. In some embodiments, the processing devicecomprises the PPU 202 or a CPU core. The worker threads concurrentlyfill their command lists by making API calls (e.g., state changes, drawcommands, etc.) into the driver. As command lists are completed, thecommand lists are handed to the master thread, which orders them andsubmits them to the driver/hardware. In some embodiments, command listsmay be submitted multiple times.

At least at first glance, implementing this model requires that thedriver be “stateless,” meaning that any device driver interface (DDI)entry point can be fully handled and translated into methods withoutreference to the “current” API or processor state. In one embodiment,each DDI entry point could simply be encoded into a command token andargument data, which would be appended to a buffer associated with thecommand list. When the command list is scheduled for execution, thesetokens could be interpreted and converted to methods/commands in thepushbuffer. However, this approach suffers from bottleneck issues in themulti-threaded command list generation since much of the processing workneeded to achieve this result would still occur serially in a singlethread.

In one embodiment, each command list includes of a tokenized commandqueue, as well one or more associated GPU-readable command buffersegments. Many DDI entry points are stateless, and would just append tothe command buffer. One of the command tokens could be “append the nextN command buffer bytes.” Other commands may be required forstate-dependent processing. For example, this processing could happen onthe master thread when the command list is submitted, and its resultsspliced into the method stream seen by the hardware.

In one embodiment, each command list inherits any state left over fromthe command list executed before the current command list is executed.This means that while the command list is being generated, the initialstate may not be known and that state might even be different each timethe command list is executed, i.e., if the ordering of command listschanges. In this case, the driver does not always know the current APIstate at all times while building a command list.

In one embodiment, an indirection is inserted between resourcereferences in a command list and the actual resources that the commandlist uses. The binding of references to the real resources happens whenthe command list is submitted, and could change between submissions.

FIG. 5 is a conceptual diagram illustrating multi-threaded processingusing parallel command lists, according to one embodiment of theinvention. As shown, a software application written by an applicationdeveloper may be divided into multiple threads 512-1, 512-2, 512-3. Eachthread 512-1, 512-2, 512-3 is associated with a different driver 504-1,504-2, 504-3, respectively. Each driver 504-1, 504-2, 504-3 isassociated with a different command list 506-1, 506-2, 506-3,respectively. The threads that build the command lists are executed onCPU cores as determined by the application and operating system. Oncethe threads have completed building their command lists, the commandlists are submitted or scheduled for execution by the processing unit510, such as a GPU. The command list submission step is performed viathe software multiplexor 508 at the control of the application 502 viasignal 514.

FIG. 6 is a conceptual diagram that illustrates state inheritance acrosscommand lists, according to one embodiment of the invention. Asdescribed, when implementing state inheritance across command lists, aproblem may arise when the state is set near the end of the execution ofone thread and a command that depends on the state is to be executednear the beginning of another command list. An example of a command thatdepends on the state is a draw command.

In the example shown in FIG. 6, let us assume that command list 506-1 isexecuted first, followed by executing command list 506-2. As shown inFIG. 6, a state of the processing unit 510 is set by one or morecommands 604 near the end of executing command list 506-1. Whenimplementing state inheritance across command lists, the state of theprocessing unit 510 is carried over to the execution of command list506-2, indicated by path 602. A draw command 606 may be included incommand list 506-2 near the beginning of the command list 506-2. Sincethe threads 512-1 and 512-2, associated with command buffers 506-1 and506-2, respectively, may be unrelated threads, carrying over the stateto thread 512-2 may cause errors when no remedial action is taken toensure that the state is set properly when the draw command 606 isexecuted. As described in greater detail herein, embodiments of theinvention allow for state inheritance across command lists to beimplemented efficiently and without errors.

FIG. 7 is a conceptual diagram illustrating a command list 706 for stateinheritance, according to one embodiment of the invention. The commandlist 706 may include a series of tokens. In one embodiment, each tokenis associated with a pointer to a buffer of commands.

In some embodiments, the command list 706 alternates between a tokenassociated with application commands and a token associated with patchmethods, as described herein. In the embodiment shown in FIG. 7, thetokens in command list 706 comprise pointers to buffers 702, 704.Buffers 702, 704 each store commands, also referred to as “methods,” tobe executed by an execution unit, such as, e.g., PPU 202 or a CPU core.In one embodiment, buffer 702 includes “regular” application commandsincluded in the thread to be executed, and buffer 704 includes “patch”methods that are utilized to set the processor state to the appropriatestate for subsequent commands executed by the processing unit.

In some embodiments, a driver is configured to set the pointers includedin the command list 706 and store commands in the buffers 702, 704. Thedriver sequentially walks through the commands in the thread, and storesthe commands that are executed using the current processor state inblock A in buffer 702. Once the driver encounters a command that dependson a different processor state, the driver stops storing commands inblock A. Instead, the driver stores one or more patch methods at blockx₀ in buffer 704, where the commands/methods stored in block x₀ areconfigured to modify the processor state into the form expected bysubsequent commands in the thread. Once the patching methods are storedin buffer 704, the driver continues to store commands included in thethread in buffer 702 at the next available block, i.e., block B. Thisprocess is repeated until all of the commands in the thread are storedin buffer 702 and the required patch methods are stored in buffer 704.

At execute, the processing unit encounters a block of patch commands andgenerates a patch. The patch is then inserted into the command queue.While building the command list, the driver only writes into buffers 702and 706. The “patch” entries in 706 describe what kind of stateinformation is needed by the subsequent entries. When a command list issubmitted for execution—typically on a master thread—the patch entriesare used to write the patch methods into buffer 704. The insertion intothe command queue is virtual: the command queue is just a sequence ofpointers to buffer segments containing methods, so it would point tosegments {A, x0, B, x1, . . . }.

As shown, the command list 706 alternates between pointers to commandsto be executed and patch methods. Pointers stored in the command list706 point to either blocks of thread commands in buffer 702 or blocks ofpatch methods in buffer 704. As also shown, the blocks in buffer 704and/or buffer 702 can be reused on subsequent passes through the commandlist. For example, as shown, on a first pass, a particular patch methodpointer in the command list 706 may point to block x₀, but on asubsequent pass, the same pointer may point to block x₂. Using theexample shown in FIG. 7, the sequence of blocks to be executed by theprocessing unit may be, for example:

>A,x₀,B,x₁,C . . . A,x₂,B . . . .

In some embodiments, better efficiency is achieved when there are fewerpatches and each patch is as small as possible, i.e., fewercommands/methods per patch. Some embodiments of the invention includeone or more commands, described below, that are configured to moreefficiently perform the state patching described above. Accordingly,embodiments of the invention are associated with adding one or moreadditional parameters to the “state” of the processing unit, andproviding hardware-based techniques for modifying the one or moreadditional parameters.

1. Index Buffer Format

In one embodiment, index buffer format is added as a parameter ofprocessor state in the hardware. For example, when the hardware draws anindex triangle list, the index may be a 16-bit or 32-bit index. Inconventional approaches, such as DX11, older hardware required indexsize to be encoded in the draw method since the draw command depends onthe index size. Accordingly, in DX 11, a patch is required for each drawcommand encountered.

Instead, embodiments of the invention include index buffer format as aparameter of processor state. Thus, a draw command does not need toinclude the index size with the draw command. The processing unit cansimply reference the state parameter associated with index buffer formatwhen executing the draw command. To modify the state parameterassociated with index buffer format a single SetIndexBuffer( ) methodthat has an IndexSize field may be implemented.

2. Primitive Topology

In conventional approaches, primitive topology was not included as partof the processor state in the hardware. Thus, for each draw command, theprimitive topology (e.g., triangles, triangle strip, lines, etc.)associated with the draw command would need to be included in the drawcommand. According to embodiments of the invention, the primitivetopology is added as a state parameter and does not need to be includedas part of the draw command. However, the current setting of theprimitive topology parameter may not be known to the processing unitwhen the processing unit receives a draw command. Embodiments of theinvention, therefore, implement a single method SetPrimitiveTopology( )to set the primitive topology, rather than requiring the driver toinclude the primitive topology as part a draw command (or part of theBegin method).

3. User Clip Plane Enables

Certain programmable shader units that process vertices allow a user towrite up to N different clip distance outputs. For example, N may beequal to 8. To perform clipping, the shader unit may evaluate a positionof a vertex relative to a particular clip plane. Each clip plane splitsup the scene into areas where vertices should be drawn and areas wherevertices should be cut away and not drawn. If a vertex has a positivevalue relative to the clip plane, then the vertex is on the “right” sideof plane and should be drawn. If a vertex has a negative value relativeto the clip plane, then the vertex is on the “wrong” side of plane andshould not be drawn.

As described, in one embodiment, one or more shader stages in a geometryprocessing pipeline could write clip distances. The clip distanceswritten by the last enabled shader stage are used for clipping; clipdistances written by prior stages are simply inputs to their subsequentstage. When implementing state inheritance across command lists,different threads can “hook up” or utilize different shaders.Accordingly, embodiments of the invention provide techniques forautomatically determining which is the last shader used. Based on theclipping information associated with that shader, the hardware candetermine which clip distances have been written (i.e., are candidatesfor being clipped to). With state inheritance across command lists,while the driver is building a command list, the driver does not knowwhich stages are enabled. Thus, the driver does not know what is thelast enabled stage. The driver, therefore, cannot tell the hardware theclip distances of which stage to use for clipping.

Additionally, in some embodiments, an enable bit may be associated witheach of the N different clip distance outputs associated with aparticular command. This set of N enable bits can be logically ANDEDwith the clipping information associated with the last shader used toconfigure the shader.

For example, a programmable processing pipeline may include a vertexshader that processes points and determines the position of the vertex,and a geometry shader that operates on full primitives. In a firstconfiguration, the programmable processing pipeline may be configured sothat the geometry shader is invoked after the vertex shader in thepipeline. Accordingly, the clip distances are set by the last stage,i.e., the geometry shader. In a second configuration, the programmableprocessing pipeline may be configured to that the geometry shader is notinvoked after the vertex shader in the pipeline (i.e., null geometryshader). In the second configuration where there is no geometry shader,the clip distances are set by the vertex shader. Embodiments of theinvention, therefore, implement a single method SetUserClipEnable( )that includes a separate enable bit for each user clipping plane. Asdescribed, this set of N enable bits can be logically ANDED with theclipping information associated with the last shader used.

4. Predicating Rendering Override

Sometimes the driver needs to push/pop predication state for “internal”blits, such as shader/texheader/sampler upload or for operations thatare supposed to ignore predication. For example, the driver may need todo internal draw calls to accomplish certain actions that do notcorrespond to draw commands from the application.

Accordingly, the current predication state needs to be known in order torestore it following the internal operations. Embodiments of theinvention add a SetRenderEnableOverride( ) method to the API to overridethe current predication state, giving us a one level stack for push/popof the predication state.

FIG. 8 is a flow diagram of method steps for multi-threaded processingwith state inheritance across command lists, according to one embodimentof the invention. Persons skilled in the art will understand that, eventhough the method 800 is described in conjunction with the systems ofFIGS. 1-7, any system configured to perform the method steps, in anyorder, is within the scope of embodiments of the invention.

As shown, the method 800 begins at step 802, where a driver executed bya processor receives an application program that includes multipleparallel threads. As described in FIG. 5, the application program may bewritten by an application developer. At step 804, the driver generates acommand list for each thread. As described above in FIG. 7, each commandlist may alternate between pointers to a buffer of application commandsand pointers to a buffer of patch methods. Step 804 is described ingreater detail in FIG. 9, below.

At step 806, a processing unit executes the commands included in a firstcommand list associated with a first thread. In some embodiments, theprocessing unit executes the commands utilizing one or more processingstages included in a processing pipeline. For example, as shown in FIG.7, the processing unit receives commands included in various buffers702, 704. The processing unit may first execute the application commandsin block A from buffer 702, then execute the patch methods in block x₀from buffer 704, then execute the application commands in block B frombuffer 702, and so on. At the end of the command list, the processingunit stops executing commands from the first thread's command list andswitches to executing commands from a second thread's command list.

At step 808, a driver maintains the processor state when the processingunit stops executing commands from the first thread's command list. Asdescribed, the processor state is defined as the set of parametersassociated with a processing unit that executes commands. Examples ofparameters included in the processor state include a selection of avertex shader, a geometry shader, a pixel shader, or the like, a set ofdifferent textures bound to a pixel shader, a parameter defining howblending is performed, a list of target rendering surfaces, amongothers. At step 810, the processing unit executes the commands includedin a second command list associated with a second thread. Step 810 issubstantially similar step 806 described above. Accordingly, theprocessor implements state inheritance across command lists.

FIG. 9 is a flow diagram of method steps for generating a command list,according to one embodiment of the invention. Persons skilled in the artwill understand that, even though the method 900 is described inconjunction with the systems of FIGS. 1-7, any system configured toperform the method steps, in any order, is within the scope ofembodiments of the invention.

As shown, the method 900 begins at step 902, where the driver receives acommand included in a thread of application commands. As described inFIG. 5, the application program may be written by an applicationdeveloper and may include multiple parallel threads. As described inFIG. 8, at step 804, a command list is generated for each of theparallel threads.

At step 906, the driver determines whether the command can be encodedusing only the known state of the processor. What matters is whether thedriver knows enough about the execution-time processor state to generatethe methods (i.e., hardware representation of the command). Some methodscan be written without knowing any other processor state. Other methodsdepend on other processor state, but that processor state is known asthe driver is building the command list. Either of these can be writteninto the command buffer immediately during command list construction. Ifthe encoding of a method depends on other state, and that state is notknown while constructing the command list, then that method cannot bewritten to the command buffer at this time—it must be deferred until thecommand list is executed and the execution-time state is known.

If the driver determines that determines that the command can be encodedusing only the known state of the processor, then the method 900proceeds to step 906. At step 906, the driver inserts the command into afirst command buffer associated with application commands. As shown inFIG. 7, the first command buffer, i.e., buffer 702, may be divided intoblocks of application commands. A pointer to the appropriate block ofapplication commands is then added to the command list.

At step 908, the driver determines whether more commands are included inthe thread. If more commands are included in the thread, then the method900 returns to step 902, described above. The method 900 walks througheach application command included in the thread when generating thecommand list. If no more commands are included in the thread, then themethod 900 terminates.

If, at step 904, the driver determines that the command cannot beencoded using only the known state of the processor, then the method 900proceeds to step 910. At step 910, the driver stores information aboutwhat patch methods will be needed into a side-band queue. The queue islater processed and the patch methods are written when the command listis executed. For example, making index size an independent stateparameter avoids the need for a patch. When index size is encoded indraw methods, then any draw command issued when the index size isunknown would need to be patched later. The goal is to reduce the numberof patches.

In sum, embodiments of the invention provide techniques for implementingstate inheritance across command lists. Each command list alternatesbetween pointers that point to application commands and pointers thatpoint to patch methods. The patch methods are inserted in the commandlist any time an application command is encountered that depends onprocessor state that is unknown during command list construction.

Advantageously, better processing efficiency is achieved relative toprior art techniques that do not provide state inheritance acrosscommand lists. Since the processor does not need to be reset to the“clean-slate state” each time a different thread is executed, lessprocessing overhead is required.

UnbindAll Method

As described above, DX11 does not allow processor state inheritanceacross command lists. Instead, the processor state is reset at thebeginning of every command list to a so-called “clean slate state.” Thatmeans that each user-mode driver thread sets all the state parameters inthe processor at the beginning of the command list. In DX11, the addedprocessing cost of resetting the processor state to the clean slatestate using dozens or hundreds of commands adds inefficiencies to thesystem, thereby reducing overall performance.

In one embodiment, the clean slate state is essentially a set of initialconditions for all class method state where no resources are bound,e.g., no texture headers, no texture samplers, no constant buffers, andno render targets. In DX11, at the beginning of each command list, thedriver will insert all the state-setting methods, to set the initialconditions. In the DX, all resources are unbound slot-by-slot, whichtakes 819 individual methods:

(5 shader types)*((128 texture header bind methods per shader type)+(16sampler bind methods per shader type)+(18 constant buffer bind methodsper shader type))+(9 target “bind” methods)=819 methods

Executing 819 methods each time a different command list is executedtakes up a lot of processing resources. Accordingly, embodiments of theinvention implement a UnbindAll( ) method that unbinds everything withone method. Implementing this method increases performance of the driverand reduces the required bandwidth for methods in to the GPU.

In one embodiment, each state parameter, such as texture headers, arestored in different rows of a memory unit. To implement the UnbindAll( )method, a valid bit is appended to each row of the memory unit. Tounbind all the state parameters, each valid bit is set to an invalidstate.

In another embodiment, if the state parameters are stored in a cachememory, the UnbindAll( ) method may be implemented by zero-ing out oneor more cache lines in the cache memory. In yet another embodiment, ifthe state parameters are stored in a banked memory, the UnbindAll( )method may be implemented by clearing out one or more banks at once.

FIG. 10 is a flow diagram of method steps for implementingmulti-threaded processing using an UnbindAll( ) method, according to oneembodiment of the invention. Persons skilled in the art will understandthat, even though the method 900 is described in conjunction with thesystems of FIGS. 1-7, any system configured to perform the method steps,in any order, is within the scope of embodiments of the invention.

As shown, the method 1000 begins at step 1002, where a driver receivesan application program that includes multiple parallel threads. At step1004, the driver generates a command list for each thread. At step 1006,a processor executes commands associated with a first command list thatis associated with a first thread. Steps 1002, 1004, and 1006 may besubstantially similar to steps 802, 804, and 806, respectively,described above.

At step 1008, the processor executes an UnbindAll( ) method included ina second command list associated with a second thread. As described, theUnbindAll( ) method unbinds all of the state parameters with one method.In one embodiment, the UnbindAll( ) method may be inserted as the firstmethod in each command list. In another embodiment, the UnbindAll( )method may be inserted as the last method in each command list. At step1008, the processor executes the remaining commands associated with thesecond command list. Step 1010 may be substantially similar to step 810,described above.

One embodiment of the invention may be implemented as a program productfor use with a computer system. The program(s) of the program productdefine functions of the embodiments (including the methods describedherein) and can be contained on a variety of computer-readable storagemedia. Illustrative computer-readable storage media include, but are notlimited to: (i) non-writable storage media (e.g., read-only memorydevices within a computer such as CD-ROM disks readable by a CD-ROMdrive, flash memory, ROM chips or any type of solid-state non-volatilesemiconductor memory) on which information is permanently stored; and(ii) writable storage media (e.g., floppy disks within a diskette driveor hard-disk drive or any type of solid-state random-accesssemiconductor memory) on which alterable information is stored.

The invention has been described above with reference to specificembodiments. Persons skilled in the art, however, will understand thatvarious modifications and changes may be made thereto without departingfrom the broader spirit and scope of the invention as set forth in theappended claims. The foregoing description and drawings are,accordingly, to be regarded in an illustrative rather than a restrictivesense.

1. A method for providing state inheritance across command lists in amulti-threaded processing environment, the method comprising: receivingan application program that includes a plurality of parallel threads;generating a command list for each thread of the plurality of parallelthreads; causing a first command list associated with a first thread ofthe plurality of parallel threads to be executed by a processing unit;and causing a second command list associated with a second thread of theplurality of parallel threads to be executed by the processing unit,wherein the second command list inherits from the first command liststate associated with the processing unit.
 2. The method of claim 1,wherein the first command list includes tokens that alternate betweenmethods in a command buffer written during command list construction andmethods in a patch method buffer written during submission of thecommand list for execution.
 3. The method of claim 2, wherein each tokencomprises a pointer to a memory unit configured to store commands to beexecuted by the processing unit.
 4. The method of claim 2, wherein indexsize is a parameter of the state associated with the processing unit,and a draw command based on the index size is included in the commandbuffer without a corresponding patch method.
 5. The method of claim 2,wherein primitive topology is a parameter of the state associated withthe processing unit, and a draw command based on the primitive topologyis included in the command buffer without a corresponding patch method.6. The method of claim 2, wherein each shader stage in a geometryprocessing pipeline has an associated set of clip plane enable bits, andthe processing unit is configured to use the clip plane enable bitsassociated with the last enabled shader stage.
 7. The method of claim 1,wherein the processing unit comprises a graphics processing unit.
 8. Acomputer-readable storage medium storing instructions that, whenexecuted by a processor, cause a computer system to provide stateinheritance across command lists in a multi-threaded processingenvironment, by performing the steps of: receiving an applicationprogram that includes a plurality of parallel threads; generating acommand list for each thread of the plurality of parallel threads;causing a first command list associated with a first thread of theplurality of parallel threads to be executed by a processing unit; andcausing a second command list associated with a second thread of theplurality of parallel threads to be executed by the processing unit,wherein the second command list inherits from the first command liststate associated with the processing unit.
 9. The computer-readablestorage medium of claim 8, wherein the first command list includestokens that alternate between methods in a command buffer written duringcommand list construction and methods in a patch method buffer writtenduring submission of the command list for execution.
 10. Thecomputer-readable storage medium of claim 9, wherein each tokencomprises a pointer to a memory unit configured to store commands to beexecuted by the processing unit.
 11. The computer-readable storagemedium of claim 9, wherein index size is a parameter of the stateassociated with the processing unit, and a draw command based on theindex size is included in the command buffer without a correspondingpatch method.
 12. The computer-readable storage medium of claim 9,wherein primitive topology is a parameter of the state associated withthe processing unit, and a draw command based on the primitive topologyis included in the command buffer without a corresponding patch method.13. The computer-readable storage medium of claim 9, wherein each shaderstage in a geometry processing pipeline has an associated set of clipplane enable bits, and the processing unit is configured to use the clipplane enable bits associated with the last enabled shader stage.
 14. Thecomputer-readable storage medium of claim 8, wherein the processing unitcomprises a graphics processing unit.
 15. A computer system, comprising:a processor; and a memory storing instructions that, when executed bythe processor, cause the processor to providing state inheritance acrosscommand lists in a multi-threaded processing environment by performingthe steps of: receiving an application program that includes a pluralityof parallel threads, generating a command list for each thread of theplurality of parallel threads, causing a first command list associatedwith a first thread of the plurality of parallel threads to be executedby a processing unit, and causing a second command list associated witha second thread of the plurality of parallel threads to be executed bythe processing unit, wherein the second command list inherits from thefirst command list state associated with the processing unit.
 16. Thecomputer system of claim 15, wherein the first command list includestokens that alternate between methods in a command buffer written duringcommand list construction and methods in a patch method buffer writtenduring submission of the command list for execution.
 17. The computersystem of claim 16, wherein each token comprises a pointer to a memoryunit configured to store commands to be executed by the processing unit.18. The computer system of claim 16, wherein index size is a parameterof the state associated with the processing unit, and a draw commandbased on the index size is included in the command buffer without acorresponding patch method.
 19. The computer system of claim 16, whereinprimitive topology is a parameter of the state associated with theprocessing unit, and a draw command based on the primitive topology isincluded in the command buffer without a corresponding patch method. 20.The computer system of claim 16, wherein each shader stage in a geometryprocessing pipeline has an associated set of clip plane enable bits, andthe processing unit is configured to use the clip plane enable bitsassociated with the last enabled shader stage.